The present invention relates to an application specific integrated circuit (ASIC) comprising an integrated central processor unit (CPU) (10), an integrated network interface control (NIC) (11) and at least one integrated input/output (I/O) device (13-16), and a transceiver circuit for buffering and amplifying SCSI signals from such an ASIC, whereby the outputs can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively.
Application specific integrated circuits (ASIC) for connection between a data communication network and peripheral devices traditionally comprises a central processor unit (CPU), a network interface control (NIC) and input/output (I/O) means. These I/O means are conventionally parallel or serial I/O devices. However there is a need for faster communication and the possibility to use faster communication protocols. This is especially important when the ASIC are intended for control and management of non-PC type peripherals, to make them act as independent servers on a network. There is for such ASIC""s a wish for faster communication protocols to make them cost effective.
Such faster communication protocols could be SCSI or ATA. However, these communication protocols have, never to the applicant""s knowledge, been used in ASIC""s of the above mentioned type.
The SCSI protocol is designed to provide a peer-to-peer I/O bus for data transfer with peripheral devices, such as magnetic discs, tapes, printers, processors, optical discs, magnetic tapes, CD-ROMs, scanners, medium changers, and communications devices. The SCSI-standards are described in ANSI X3.131-1994: Small Computer Systems Interface-2 (SCSI-2) and ANSI X3.277-1996: Information Technologyxe2x80x94SCSI-3 Fast-20.
Attention Attachment (ATA) is an interface protocol mainly used for memory devices, and is also called Integrated Device Electronics (IDE), and is specified in ANSI X3.279-1996: AT Attachment Interface with Extensions (ATA-2).
These communication protocols have mainly been used for personal computers and the like, and mostly with integrated transceiver circuits, where the CPU, SCSI, NIC etc. are separate circuits. This is however not applicable for smaller devices, due to the extensive increase in the production cost. For such smaller devices it is instead convenient to use external transceiver circuits for buffering and amplifying the signals. Another reason to use such external transceiver circuits is that the device becomes more portable and compatible. The device hereby does not become dependent on certain protocols, such as SCSI, but can be transferred between different technologies. Still another reason is that the signal level and power that is needed for SCSI would make it necessary to use two different modes for the pins, e.g. for ATA, if the transceiver circuit was integrated. If, however, an external transceiver circuit is used, the same signal levels can be used independently of the intended use of the device, and whereto the pins are to be connected.
A problem for such transceiver circuits is, that it has to be able to handle both the case with wired-OR and the case with active negation. In wired-OR the signal is actively driven to a low position, but is left to return to the high position without active driving. To speed up the speed of the data transfer it is possible to actively return the level to high. This is called active negation. For example with the use of SCSI it is necessary to use both wired-OR and active negation; wired-OR has to be used at least during the arbitration phase while it is preferred to use the faster active negation in the information transfer phase. It is also necessary to be able to change the direction of the bus.
A known transceiver circuit which is able to handle both the wired-OR and the active negation situation is for example the transceiver circuit SN75LBC968 from Texas Instruments. This circuit is intended to be, at one side, connected with single direction lines to an application circuit, and at the other side to double direction SCSI bus lines. However, a disadvantage with this circuit is that it uses separate pins for the connection with an application circuit for active negation transfer and for wired-OR transfer, i.e. some outputs are totem-poles and some are open-drains. This means that there is a need for twice as many data bus pins on the application circuit. There is therefore a wish for transceiver circuits and ASIC""s that uses fewer connection points, and thereby can be made easier and cheaper.
It is therefore an object of the present invention to provide an ASIC and a transceiver circuit of the above mentioned type which are cheaper and easier to produce, and that preferably can be connected to one another with fewer connections.
This object is achieved with an ASIC and a transceiver circuit according to the appended claims.
According to one aspect of the invention the object is achieved with an application specific integrated circuit (ASIC) comprising an integrated central processor unit (CPU) (10), an integrated network interface control (NIC) (11) and at least one integrated input/output (I/O) device (13-16), whereby one of the at least one I/O device is an ATA (16) or SCSI (15) device, with ports for connection to an external transceiver. Hereby it is possible to use the ATA and/or the SCSI protocol for faster communication between the ASIC and peripheral devices.
The integration of SCSI and/or ATA on an ASIC together with at least CPU and NIC provides several advantages relative to the prior art. E.g. it lowers the manufacturing cost of the circuit, the performance characteristics are improved, and the power consumption of the circuit is decreased as well as the EMI (Electro magnetic interference).
Preferably the NIC (11) is a fast ethernet interface. Hereby, it is also possible with faster network communication to and from the ASIC.
Further, the ASIC, with SCSI, preferably comprises pins for communication input and output, and whereby the same data pins are used for wired-OR and for active negation, and whereby one of the additional signals, and preferably the busy-signal, is used to drive the SCSI ID-signal during arbitration. Hereby, a construction which uses significantly fewer output and input pins are possible, which makes the ASIC easier and cheaper to produce.
To be able to communicate with peripheral devices with a SCSI bus, the ASIC need to have a SCSI unit, and there is also a need for an external transceiver unit between the SCSI bus and the ASIC.
Therefore, the invention also comprises, according to a second aspect, a transceiver circuit for buffering and amplifying SCSI signals from an ASIC of the previously described type, whereby the outputs can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively, and whereby the same data transmission lines between the transceiver circuit and the application circuit is used for wired-OR and for active negation. Preferably the BSY-signal, during the arbitration phase, also is used to drive the SCSI ID-signal on the data bus. Hereby the need for communication lines between the ASIC and the transceiver is diminished which provides for an easier and more cost effective solution.